1. Field of the Invention
The present invention relates to a method of forming a contact hole pattern in a semiconductor integrated circuit device.
2. Description of the Related Art
The progress of the recent semiconductor fabrication techniques is very remarkable, and semiconductors having a minimum processing dimension of 90 nm are presently mass-produced. Micropatterning like this is achieved due to the rapid progress in the fine pattern formation techniques, such as the mask processing technique, lithography process technique, and etching process technique.
To further advance micropatterning in the processing of a flash memory and the like, a method that achieves micropatterning at low cost by adding another technique to the conventional lithography technique has been developed.
A via hole or contact hole (these holes will be collectively referred to as contact holes hereinafter) is necessary to obtain an electrical connection between interconnections or from an interconnection to a gate or diffusion layer. A connecting portion between the contact hole and a lower interconnection layer such as a gate interconnection requires a pattern wider than interconnections in portions other than the connecting portion.
The interconnection width in this connecting portion is determined by taking account of the misalignment between the masks of the contact hole and lower interconnection layer, and the final dimensional difference between the lower interconnection layer and contact hole. This portion having a large interconnection width in the connecting portion is called a fringe.
In a similar vain, as the micropatterning of interconnections and gate patterns advances, the formation of these patterns is beginning to require the techniques called resolution enhancement techniques. Examples of these resolution enhancement techniques are Alt.PSM (Alternating Phase Shift Mask) (Levenson mask), SRAF (Sub-resolution Assist Features), and OAI (Off-Axis Illumination).
When using these resolution enhancement techniques, it is necessary to customize the illumination shape of an exposure apparatus so as to resolve only fine patterns, and use a mask whose phase, transmittance, and the like are changed. This makes it possible to ensure a sufficient lithography margin for a simple line shape, but makes it difficult to resolve other patterns.
The fringe portion described above is a pattern other than a simple line pattern. Accordingly, it is very difficult to form a fine line pattern by the resolution enhancement techniques and form the fringe portion and its vicinity with a sufficient lithography margin at the same time.
That is, when the resolution enhancement techniques are used to resolve fine patterns, it becomes difficult to secure the fringes of interconnections and gates. This makes it difficult to assure the device reliability in the contact hole connecting portion (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2006-173186).